Exemplary embodiments of the present invention relate generally to a method for fabricating a semiconductor device, and more particularly, to a method for verifying an optical proximity correction (OPC).
Semiconductor memory devices, such as dynamic random access memory (DRAM), include a large number of fine patterns. Such fine patterns are formed through a photolithography process. According to the lithography process, a target film to be patterned is coated with a resist film, and a photomask in which circuit patterns to be transferred to a wafer are formed is disposed on the resist film. Then, the circuit patterns formed on the photomask are transferred to the resist film through an exposure process and a development process, thereby forming resist patterns partially exposing the surface of the target film. Subsequently, the exposed regions of the target film are removed by an etching process using the resist patterns as a mask, and the resist patterns are then stripped. In this manner, the fine patterns of the semiconductor memory device can be formed.
In order to satisfy demands for speed, functionality and capacity, high integration of the semiconductor device is required. However, when a semiconductor device is highly integrated, the design rule is reduced and the line width becomes close to an exposure wavelength, and thus it becomes difficult to implement the patterns as arranged in the design layout. One of the reasons for difficulty in implementing the patterns as arranged in the design layout is the optical proximity effect (OPE) which occurs during the exposure process. It can be understood that the optical proximity effect is derived from pattern deformation caused by nonuniformity of energy intensity due to optical diffraction during the exposure process. Therefore, optical proximity correction is used to solve pattern deformation caused by the optical proximity effect. Optical proximity correction is the process of correcting the layout of target patterns to be transferred onto a wafer using knowledge of the optical proximity effect.
Specifically, the layout of patterns to be transferred onto the wafer is designed, and the optical proximity correction is performed on the designed layout. Then, suitability is determined by verifying the performed optical proximity correction, and the pattern layout is applied to real patterns. The verification step is a step of detecting weak points in which defects affecting the device fabrication, for example, necking defects or bridge defects, may be formed.
In the verification step, weak points vulnerable to defects are generally detected using the critical dimension (CD) of simulated patterns. In the case of using the CD of patterns, a plurality of weak points are detected. Points where real defects may be formed are determined manually by a worker. However, determining defect weak points manually has limitations, including the amount of time necessary to perform such a determination. Also, since a CD trend and a process margin trend do not always coincide with each other, the use of the CD is not always accurate in determining the weak points where defects may actually occur. That is, the accuracy of a verification model is important in order to exactly predict defect weak points, and there is a need for a system which can exactly detect the defect weak points.